Field emission display (FED) is a novel flat planar display technology, the FED has the advantages of the cathode ray tube (CRT), such as wide viewing angle, colorful, high response speed. Presently, in a variety of flat panel displays, only FED can reach the high image display quality as that of the traditional CRT. The FED also has the advantages of liquid crystal display (LCD), such as thin and slight, as well as small size, light weight, low energy consumption, long life, high image quality. The FED can be classified into diode, triode and multiple structures.
The diode structure FED is composed of anode and cathode, although the fabrication process of diode structure FED is simple, low cost, it has the problems of high drive voltage and very hard to control the uniformity of electron emission, and is not suitable for the fabrication of high quality FED.
The triode FED is composed of cathode, gate and anode, and can be classified into normal gate, under gate and planar gate structures. The triode FED uses gate to control the field emission of cathode, while not the high voltage as for the diode FED.
In the following, we will provide the descriptions of normal gate, under gate and planar gate structured FED with the aides of some drawings.
FIG. 1 shows the scheme of cross-section of normal gate FED, cathode conducting layer 013, dielectric layer 014 are arranged on the back glass substrate 011, gate conducting layer 015 is arranged on the dielectric layer 014, anode conducting layer 018 is arranged on the fore glass substrate 010, phosphor layer 017 is arranged on the anode conducting layer 018. The fore substrate and back substrate are face to face aligned and packaged, whose distance is maintained and fixed by the spacers 012. The normal gate FED is easy for low voltage regulation, but the fabrication is complex and high cost. Usually, the fabrication of the dielectric layer and gate is followed by that of the electronic materials, so the cathode materials subject to damage and contamination during the preparation of the dielectric layer and gate.
FIG. 2 shows the scheme of cross-section of under gate FED, gate conducting layer 023 is arranged on the back glass substrate 021, dielectric layer 24 is arranged on the gate conducting layer 023, cathode conducting layer 025 is arranged on the dielectric layer 24, and the cathode conducting layer 025 is perpendicular to the gate conducting layer 023, field emission layer 026 is arranged on the cathode conducting layer 025, anode conducting layer 028 is arranged on the fore glass substrate 020, phosphor layer 027 is arranged on the anode conducting layer 028. The gate conducting layer 023 is underneath the cathode conducting layer 025, the field emission material is fabricated after the fabrication of the gate conducting layer 023 and the dielectric layer 24. The fabrication of under gate FED is relative simple and is easier to realize. However, the electron dispersion is serious, the beam spots are large, and the cross-talk of the neighbor pixels is serious. The cross-talk of the neighbor pixels can be reduced by decreasing the distance between the anode and the cathode, but it goes against the increase of the anode voltage, and the efficiency of luminescence is low.
Both the normal gate and under gate FED have the difficulties of the fabrication of the gate and the cathode. FIG. 3 shows the scheme of cross-section of planar gate FED, gate conducting layer 033 and cathode conducting layer 034 are arranged on the back glass substrate 031, field emission layer 035 is arranged on the cathode conducting layer 034, anode conducting layer 036 is arranged on the fore glass substrate 030, and phosphor layer 037 is arranged on the anode conducting layer 036. The gate conducting layer 033 and the cathode conducting layer 034 are on the same plane and are parallel to each other, and can be fabricated at one time. The gate and cathode of the planar gate FED are parallel on the same plane, so it is needless of fabrication of dielectric layer between the gate and the cathode to avoid their short circuit, the fabrication is simple, but the dispersion of electrons is serious, and the beam spots are large, moreover, it needs to scan the high anode voltage to control image.
On the other hand, FED is a vacuum device, which needs some kind of supporting scaffold for isolation. The current technology is limited to fabricate the supporting structure alone; leading to the problems of distribution and placement of spacers.
In a word, it is necessary to develop a novel structured FED, whose fabrication processes of cathode and gate are simple, and controlled by a low voltage, the placement of spacers between the two substrates is also easy, at the same time, it can easily control the cross-talk between the two neighbor pixels caused by the electron dispersion.